Pixels for ATLAS Upgrades

Sebastián Grinstein


The Pixel group develops new silicon detector technologies for high energy physics experiments and other applications. After making key contributions to the ATLAS IBL and AFP sub-detectors the group aims to play a leading role in the HL-LHC upgrades.


Introduction

The IFAE pixel group aims to make major contributions to the ATLAS upgrade effort towards the high-luminosity LHC period. During 2018 the Pixel group has advanced in the following areas: 3D Pixel Sensors for the HL-LHC, Low Gain Avalanche Detectors and CMOS Monolithic devices for the ATLAS HL-LHC upgrade.

3D Pixel Sensors for the HL-LHC

The RD53A ASIC, a first prototype chip for the ATLAS ITk Pixel upgrade for the HL-LHC became available in 2018. CNM produced 3D sensors compatible with the new chip. The group carried out the hybridization and assembly of the first 3D RD53A devices. Later the group performed the first studies of these devices before and after irradiation. The ultimate tests will be performed with 3D sensors that are being fabricated now at CNM and that comply fully with the ATLAS specifications.

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Figure 1


Low Gain Avalanche Detectors (LGAD)

During 2018 the group made important advancements in the HGTD activities. In-deep studies of LGAD sensors before and after irradiation to understand the limitations of the technology were carried out. These studies include performance of different bulk-doping options in terms of gain and timing resolution in laboratory and beam tests, and also voltage stability and geometry optimization. Furthermore, the first ALTIROC1 devices (with a 5x5 pixel matrix) were fully assembled at IFAE with CNM and HPK LGAD sensors and are being studied now. The group is leading the digital design of the final HGTD readout chip (the ALTIROC2). Finally members of the group are responsible of the HGTD TDR preparation, due in 2019.

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Figure 2


CMOS Monolithic devices

In the context of the CMOS effort of ATLAS for the HL-LHC, the group has participated in the design of various prototypes during 2018. But the main accomplishment was the design and production of the LF2 ASIC (in the LFoundry 150 nm technology). The LF2 is a 5x5mm2 ASIC that includes two matrices with 50x50um2 pixels. One, intended for HEP is based on the FE-I3 readout scheme and the other is a photon counter. This is the first monolithic photon counter produced in a depleted CMOS technology. The early tests of the device, using a readout system fully developed at IFAE, indicate that both front-ends are operational.

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Figure 3