ATLAS Pixels

The ATLAS pixel detector upgrade activities for the High-Luminosity LHC are progressing toward the production phase. IFAE is responsible for fabricating and testing the innermost pixel modules of the barrel region (known as linear triplets). During 2025, the first production modules featuring the final readout chip (the ITkPixV2 ASIC) were assembled in the cleanroom. These modules were later subjected to demanding tests in the gray room, including evaluations with external radioactive sources, and were successfully tested in IFAE’s cleanrooms. Some triplets were also tested before and after irradiation with particle beams at CERN. IFAE is scheduled to produce approximately 130 linear triplet modules (accounting for yield) throughout 2026 and into early 2027. An IFAE postdoc, Krishanan Rama, is co-coordinating the 3D module activities in ATLAS.

As part of the HL-LHC upgrade, the ATLAS experiment will install a new High Granularity Timing Detector (HGTD) between the forward and central calorimeters. The HGTD will precisely measure the time associated with particles produced in HL-LHC proton-proton collisions. During 2025, IFAE fabricated more than 100 ALTIROC3 modules and the first ALTIROC-A modules implementing the final design for the detector. The hybridization and module pre-production phases started toward the end of 2025. IFAE is playing several key coordinating roles within HGTD, specifically in hybridization, module fabrication, and performance. Module loading activities also advanced, with various prototypes featuring glass devices and ALTIROC3 chips being loaded into detector units. In parallel, the group continued improving Alvin, the HGTD module readout system developed by IFAE. Alvin is used for device characterization in various labs and is fundamental for the test-beam DAQ. During 2026, pre-production activities will ramp up.

Depleted Monolithic Active Pixel Sensors (DMAPS) integrate both the sensor and front-end electronics on a single substrate, eliminating the need for a complex sensor-to-chip interconnection process. Modern CMOS technologies provide good radiation tolerance, making DMAPS an attractive alternative for tracking detectors in High Energy Physics (HEP). IFAE has been working on the design and characterization of DMAPS for the last ten years. Recently DMAPS are increasingly being explored for timing measurements. IFAE, in collaboration with IRFU (France), designed a new prototype using LFoundry 150 nm HV technology: the Mini-CACTUS-V2 chip. This chip features an improved pre-amplifier design aimed at enhancing jitter performance and reducing recovery time. The chip was characterized in several test-beam campaigns at CERN in 2025, enabling a detailed assessment of the performance of the different amplifier configurations and pixel geometries implemented in the prototypes. Outstanding timing performance for a pixel detector without internal gain was achieved with 0.5 × 0.5 mm² pixel cells, reaching a time resolution below 50 ps at bias voltages above 300 V. A best time resolution of 45 ps was measured at a bias voltage of 450 V.